The present invention relates generally to the art of electronic packaging and more specifically relates to methods of making compliant semiconductor chip packages.
Modern electronic devices utilize semiconductor chips, commonly referred to as “integrated circuits” that incorporate numerous electronic elements. These chips are typically mounted on substrates, such as printed circuit boards, which physically support the chips and electrically interconnect each chip with other elements of the circuit. The substrate may be a part of a discrete chip package used to interconnect a single chip to external circuits or may be a “module” whereby one or more chips are mounted directly to a substrate which interconnects the chips with other circuit elements mounted to the substrate. In either case, the semiconductor chip(s) must be securely assembled with the substrate and must have reliable electrical interconnection(s) to the substrate.
Advanced semiconductor chips may require hundreds of input/output (“I/O”) connections and the substrate must accommodate all of the required external electrical interconnections to the chip. Structures connecting the chip to the substrate ordinarily are subject to substantial strains caused by thermal cycling as temperatures within the chip package change during operation. Typically, the chip and the substrate expand and contract by different amounts. This causes the electrical contacts on the chip to move relative to the electrical contact pads on the substrate, thus deforming the electrical interconnections between the chip and substrate and placing them under mechanical stress. These repeated stresses can cause breakage of the electrical interconnections.
U.S. Pat. Nos. 5,148,265 and 5,148,266, the disclosures of which are hereby incorporated by reference herein, solve these problems by providing a flexible, sheet-like interposer including conductive terminals and flexible leads connected to and extending from the terminals. This flexible layer is mounted over the face of a semiconductor chip, preferably with a soft, compliant material disposed beneath the flexible layer and the terminals. The conductive terminals are electrically connected to electrical contacts on the semiconductor chip by the flexible leads. The conductive terminals can be connected or bonded to contact pads on a substrate so as to connect the semiconductor chip to the substrate. Because the terminals are moveable with respect to the contacts on the semiconductor chip, the assembly compensates for thermal expansion. Also, because the terminals are compliant or moveable in the vertical directions normal to the face of the chip, the terminals can be readily engaged with a test probe before assembly to the substrate. Thus, the subassembly can be tested prior to assembly to the substrate.
Commonly assigned U.S. Pat. No. 5,548,091, the disclosure of which is hereby incorporated by reference herein, discloses a prefabricated interposer or connection component for a semiconductor chip. The connection component includes a flexible dielectric film having top and bottom surfaces and further includes conductive terminals accessible at a surface of the dielectric film and flexible leads extending from the terminals. The connection component further includes an adhesive disposed on the bottom surface of the flexible dielectric film for bonding the bottom surface of the dielectric film to the semiconductor chip. The adhesive desirably is solid and non-tacky at temperatures below a preset activation temperature, but is adapted to reach a flowable condition upon heating to above the preset activation temperature, and to form a bond after such heating. Preferably, the adhesive is adapted to form a relatively weak bond to the bottom surface of the dielectric film or to the surface of the chip. Thus, the connection component can be removed from a chip after bonding thereto. This greatly facilitates repair and reclaim of chips from subassemblies which prove to be defective when tested. Such defective subassemblies may arise, for example, where there is a fault in the connection component or the bonding process.
For example, commonly assigned U.S. Pat. No. 5,659,952, the disclosure of which is hereby incorporated by reference herein, discloses a method of fabricating a compliant interface for a semiconductor chip typically comprised of a compliant encapsulation layer having a controlled thickness. In certain preferred embodiments of the '952 Patent, a connection component, such as a flexible, substantially inextensible dielectric film, is provided. A compliant element, such as a plurality of compliant pads defining channels therebetween, is attached to a first surface of the first support structure. The compliant pad/connection component subassembly is then assembled with a semiconductor chip having a front face including a plurality of contacts. During assembly, the front face of the semiconductor chip is abutted against the compliant pads and the contacts are electrically connected to corresponding terminals on a second side of the dielectric film. A curable liquid encapsulant material, such as a curable silicone elastomer, is then provided between the semiconductor chip and the dielectric film and around the compliant pads while the chip and the dielectric film are held in place. The liquid encapsulant is then cured, whereby the compliant pads and the cured encapsulant provide a substantially continuous compliant interface between the semiconductor chip and the flexible dielectric film.
The above-referenced '697 application discloses a method of encapsulating a semiconductor chip package. According to preferred embodiments of the '697 application, a semiconductor chip package assembly has a compliant element or spacer layer between the top surface of a flexible dielectric film and the contact bearing surface of a semiconductor chip. The flexible dielectric film has conductive leads thereon, the leads having first ends which are electrically connected to the terminals and second ends which are bonded to the respective chip contacts. A protective layer is attached on a bottom surface of the dielectric film to cover the terminals on the substrate and to seal any apertures in the dielectric film. After attachment of the protective layer, a flowable, curable encapsulant material is deposited around at least a portion of a periphery of the semiconductor chip so as to encapsulate the conductive leads. The protective layer prevents the curable encapsulant from flowing through any dielectric film apertures. The encapsulant material is then cured or at least partially cured to allow for handling and/or further processing.